The present invention relates to a non-volatile semiconductor memory device and, more particularly, to a non-volatile semiconductor memory element having floating and control gates.
In general, E.sup.2 PROM (Electrically Erasable and programmable Read Only Memory) has been known as a non-volatile semiconductor memory element which can be programmable and erased electrically. One bit of an E.sup.2 PROM is generally constituted with one select transistor and one memory cell transistor, and the memory cell transistor has floating and control gates.
Referring to FIG. 22, such a memory cell of the E.sup.2 PROM is shown, in which a reference numeral 301 depicts a P-type silicon substrate, 302-1 to 302-3 an N-type impurity diffusion layer of a source/drain region, 303 a gate electrode of the select transistor, 304 a floating gate electrode of the memory cell transistor, 305 a control gate electrode of the memory cell transistor, 306 a tunnel insulating film formed between the floating gate electrode and the N-type impurity diffusion layer region 302, 306 a first gate insulating film between each of the gates 303 and 304 and the corresponding portion or channel portion of the substrate, and 307 a gate insulating film.
Programming of data into this memory cell is performed as follows: A high voltage such as 20V is applied to the control gate electrode 305 and the drain region 302-2 is grounded. At this time, an intense electric field is applied to the tunnel insulating film 306 by capacitive coupling among the diffusion layer 302-2, the floating gate 304 and the control gate 305, so electrons are injected from the diffusion layer 302-2 to the floating gate 304 by F-N (Fowler-Nordheim) tunneling to negatively charge the floating gate 304. A threshold voltage of the memory cell transistor is thereby pushed up to 7V or higher. The memory cell transistor thus programmed maintains an OFF state even when being supplied at the control gate 305 with a read voltage such as 5V.
In contrast, the control gate electrode 305 is grounded and a high voltage such as 20V is applied to the gate 303 of the select transistor and the drain region 302-2 in order to erase the data. In this case, an intense electric field is applied to the gate 303 of the select transistor and the drain region 302-2 in a reverse direction to that in the case of the programming operation, so that the electrons are discharged from the floating gate electrode 304 to the diffusion layer 302-2 by F-N tunneling to positively charge the floating gate 304. Thus, the memory cell transistor is changed to a depletion state to take the threshold voltage of -3V to -5V. Therefore, the memory transistor thus becomes conductive in response to the read voltage.
Since a relatively high voltage is needed to program and erase the memory transistor as described above, transistors which are used in peripheral circuits for data programming and erasing control circuits are required to have structures durable against such a high voltage. In general, such a high voltage durable transistor needs a large area.
It is therefore desirable to perform data programming and erasing operation with a lowered voltage.